1. Field of the Invention
The present invention relates to a method for arranging a tree-type clock signal distributing circuit in a synchronous integrated circuit.
2. Description of the Related Art
Recently, as the speed of integrated circuits has been increased, a timing margin between functional blocks such as flip-flops within the integrated circuits has become critical. In order to avoid a critical condition regarding a time margin, a clock signal is introduced into an integrated circuit, so that all of the functional blocks can be almost simultaneously operated, thus realizing a so-called synchronous integrated circuit.
Even in such a synchronous integrated circuit, when the integration is very advanced, the structure becomes very fine, and the chip area is enlarged, so the resistance of connections for transmitting the clock signal and the capacitance of input nodes of the functional blocks for the clock signal have been both increased. As a result, the delay of the clock signal to the functional blocks fluctuates in accordance with the length of the connection and the number of fan-outs, to thereby increase the clock skew. This is an obstacle in increasing of the frequency of the clock signal.
In the prior art, the fluctuation of delay due to the length of the connections for the clock signal has been compensated for by making the connection configuration for the clock signal a special geometrical or logical configuration.
According to a first prior art method for arranging a clock signal distributing circuit in a synchronous integrated circuit, a main wide connection having a small resistance is arranged at a center of the integrated circuit, and a number of side branch connections are arranged between the main wide connection and the functional blocks, thus realizing a fish back bone shaped configuration for a clock signal distributing circuit. In the fist prior art method, however, the side branch connections are actually slim. Therefore, in order to sufficiently suppress the fluctuation of delay of the clock signal to the functional blocks, the main wide connection should be made as wide as possible, thereby increasing the chip area. Thus, the first prior art method does not contribute to the integration and the high frequency of the clock signal.
A second prior art method for arranging a clock signal distributing circuit in a synchronous integrated circuit uses a geometrical tree synthesis method, i.e., a geometrical tree-type clock signal distributing circuit where clock buffers are determined from an upstream side of the clock signal to a downstream side thereof (see JP-A-HEI2-62675, JP-A-HEI2-93917 and JP-A-HEI2-134919). This will be explained later in detail.
In the second prior art method, however, since the functional blocks are not always arranged in regular positions, the functional blocks are not always arranged near clock buffers, thereby increasing the clock skew. Also, if the functional blocks are forcibly adapted to the clock buffers, logic gate combination circuits connected to the functional blocks are not suitably arranged. Further, when the distribution of the functional blocks is not homogeneous, the result is a lot of unused clock buffers and a lot of clock buffers having a small number of fan-outs, such as a single fan-out, thereby increasing the chip area, thus reducing the integration.
A third prior art method for arranging a clock signal distributing circuit in a synchronous integrated circuit uses a logical tree synthesis method, i.e., a logical tree-type clock signal distributing circuit where clock buffers are determined from a downstream side of the clock signal to an upstream side thereof (see T. Kimoto et al., "OpenCAD Clock Tree Synthesis", NEC Technical Bulletin, Vol. 45, No. 8, pp. 16-20, 1992). That is, the functional blocks are divided into classes each having the same number of functional blocks which are located in the same neighborhood. Then, one clock buffer is arranged at a substantial center position of each of the classes, and the clock buffer is connected to the functional blocks thereof. Thereafter, the above-mentioned steps are repeated by replacing the functional blocks with the clock buffers, until the number of the clock buffers is reduced to one. Thus, the fan-outs of each clock buffer can be balanced to suppress the increase of the clock skew. This will be explained later in detail.
In the third prior art method, however, if the density of functional blocks is not homogeneous within the integrated circuit, the length of connections to the clock buffers fluctuates, so that the clock skew is increased.